//------------------------------------------------------------
//  Filename: eth_mac_rf.sv
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2020-11-28 10:42
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module eth_mac_rf #(
    parameter N_PORTS = 3
)
( 
 
    input  logic       clk_i,  
    input  logic       rstn_i, 

    output logic[47:0] mac_uni_addr,
    output logic[3:0]  mac_tx_ifg,
    output logic       mac_rx_strip,
    output logic       mac_cfg_loop,
    output logic       mac_cfg_byps,

    output logic       dma_tx_need,
    output logic       dma_rx_en  ,
    input  logic       dma_rx_busy,
    input  logic[3:0]  dma_rx_err ,
    input  logic[6:0]  dma_rx_rptr,
   
    output logic       dma_tx_en  ,
    input  logic       dma_tx_busy,
    input  logic[3:0]  dma_tx_err ,
    input  logic[6:0]  dma_tx_rptr,

    BDU_IF.Slave       cfg_slave,
    BDU_IF.Slave       lint_slave[N_PORTS] 
);  
//-------------------------------------------------------------
logic[6:0] dma_rx_wptr;
logic[6:0] dma_tx_wptr;
//-------------------------------------------------------------
assign cfg_slave.gnt = cfg_slave.req;

assign dma_rx_en     = 1'b1;
assign mac_tx_ifg    = 4'h1;
assign mac_rx_strip  = 1'b1;
assign mac_cfg_loop  = 1'b1;
assign mac_cfg_byps  = 1'b0;
assign mac_uni_addr  = 48'hda0203040506;
assign dma_tx_en     = 1'b0;

//initial begin
//    dma_tx_en = 1'b0;
//    #5200;
//    dma_tx_en = 1'b0;
//end
//-------------------------------------------------------------
always_ff @(posedge clk_i,negedge rstn_i) begin
    if(rstn_i == 0)begin 
        dma_rx_wptr <= '0; 
    end 
    else if (cfg_slave.req&cfg_slave.we&((cfg_slave.addr >> 2) == 'h1)) begin  
        dma_rx_wptr <= cfg_slave.wdata[6:0];
    end
end
//-------------------------------------------------------------
always_ff @(posedge clk_i,negedge rstn_i) begin
    if(rstn_i == 0)begin 
        dma_tx_wptr <= 'h2; 
    end 
    else if (cfg_slave.req&cfg_slave.we&((cfg_slave.addr >> 2) == 'h2)) begin  
        dma_tx_wptr <= cfg_slave.wdata[6:0];
    end
end 
//-------------------------------------------------------------
assign dma_tx_need = (dma_tx_wptr == dma_tx_rptr)?1'b0:1'b1;
//-------------------------------------------------------------
eth_mac_bd #(
    .N_PORTS         ( N_PORTS          ) ,
    .ADDR_WIDTH      ( 10               )  // 1024 bytes
)
eth_mac_bd_inst0 
( 
    .clk_i           ( clk_i            ) ,   
    .rstn_i          ( rstn_i           ) ,  
     
    .lint_slave      ( lint_slave       ) 
); 

endmodule
